1. Technical Field of the Invention
The present invention relates to a semiconductor device employing multi-layer interconnects therein, and more particularly to a semiconductor device having via holes/metals improved in terms of reliability therein for connecting upper and lower interconnect layers to each other, and further a method for manufacturing the same.
2. Description of the Related Art
Recently, in accordance with miniaturization and high integration of a semiconductor device, copper or copper alloy (hereinafter, name them generically as copper) has increasingly been employed as an interconnect material because copper has a lower resistance than that could be achieved by employing aluminum. In a case where a semiconductor device having multi-layer interconnects formed therein and employing copper as an interconnect material, for example, upper and lower interconnect layers each are formed of copper and a via metal for connecting upper and lower interconnect layers to each other is also formed of copper. However, when an interconnect layer and a via metal are formed of copper, there will be a tendency for the copper atoms of a certain interconnect to diffuse through an interlayer insulation film made of a silicon oxide or the like and to be recrystallized at around an interface between the interlayer insulation film and an adjacent interconnect just next to the certain interconnect, thereby causing a short circuit between the certain interconnect and the adjacent interconnect. Or, there will be a tendency for the copper atoms of a certain interconnect to diffuse into an impurity layer constituting an element, which is formed in a silicon substrate and positioned directly below the certain interconnect, and to impart damage to the element, whereby the certain interconnect substantially deteriorates the element's performance. In order to prevent such an unfavorable situation where copper deteriorates the performance of semiconductor device, in other words, so-called copper contamination, conventionally a barrier film has been formed at an interface where copper part and an interlayer insulation film are contact with each other to prevent diffusion of copper.
For example, Japanese Patent Application Laid-open No. 4(1992)-127527 discloses a technique in which a single layer film made of tantalum (Ta) is employed as such kind of barrier film. Furthermore, Japanese Patent Application Laid-open No. 2001-176965 discloses a technique in which a single layer film made of tantalum nitride (TaN) is employed as a barrier film. However, in the former technique, the following problem is found. That is, although tantalum is adherently bonded to copper, it is weakly bonded to an interlayer insulation film and therefore, copper interconnects layer and a tantalum barrier film are removed from the interlayer insulation film in a process step such as a CMP (Chemical Mechanical Polishing) step that is employed to form damascene interconnects. Moreover, in the latter technique, although tantalum nitride (TaN) is adherently bonded to an interlayer insulation film, it is weakly bonded to copper and therefore, a copper interconnect layer is unfavorably removed from a tantalum nitride barrier film at an interface therebetween in a CMP step.
In order to solve such problems found in the conventional techniques, a technique in which a barrier film having a laminated structure is proposed. For example, Japanese Patent Application Laid-open No. 11(1999)-307530 discloses a technique in which tantalum or an amorphous metal containing tantalum is formed between a barrier film and a copper interconnect layer to enhance adherence between copper and tantalum nitride in a case where a refractory metal consisting of a tantalum metal such as TaSiN (tantalum silicon nitride) or TaN is employed as a barrier film.
An example including multi-layer interconnects structure therein that employs a laminated barrier film consisting of Ta and TaN will be explained with reference to FIGS. 1A through 1D. The example has a dual damascene structure in which an upper interconnect layer and a via metal are simultaneously formed in an interlayer insulation film while having one-piece structure. First, as shown in FIG. 1A, a silicon substrate 201 is previously constructed such that a region of the substrate, which region is surrounded by an element isolation insulating film 203, has a specific element 202 formed therein and consisting of a gate electrode 205, an impurity layer 206 and the like. Furthermore, on a surface of the substrate 201 are formed a first interlayer insulation film 207 and in the first interlayer insulation film 207 is formed an element contact 209 made of W (tungsten) and electrically connected to the impurity layer 206. After forming a second interlayer insulation film 210 made of a silicon oxide on the first interlayer insulation film 207, a first interconnect trench 211 is formed by a photolithography technique such that a specific region of the second interlayer insulation film 210 is removed over its entire film thickness and a TaN (tantalum nitride) barrier film 213 and a Ta (tantalum) barrier film 214 are sequentially deposited by a sputtering method on an entire surface of the substrate, and further a Cu seed film 215 is deposited by a sputtering method thereon. Then, a Cu plating film 216 is formed by a plating method on an entire surface of the substrate with the aid of the Cu seed film 215 to fill the first interconnect trench 211 with the Cu plating film 216.
Thereafter, as shown in FIG. 1B, the Cu plating film 216, the Ta barrier film 214 and the TaN barrier film 213 are polished back by a CMP (Chemical Mechanical Polishing) method to flatten the surface of the substrate, thereby forming a first Cu interconnect layer 212 as a first interconnect layer.
Subsequently, as shown in FIG. 1C, a third interlayer insulation film 220 made of a silicon oxide is formed on the second interlayer insulation film 210 and a second interconnect trench 221 having a specific pattern and a predetermined depth from the surface of the third interlayer insulation film 220 is formed in the third interlayer insulation film 220 by a photolithography technique. Furthermore, a via hole 222 is formed in one or more portions of the bottom surface of the second interconnect trench 221 thus formed to thereby expose the surface of the first interconnect layer 212. Then, a TaN barrier film 225 and a Ta barrier film 226 are sequentially deposited by a sputtering method and further, a Cu seed film 227 is deposited thereon by a sputtering method. Thereafter, a Cu plating film 228 is formed by a plating method on an entire surface of the substrate with the aid of the Cu seed film 227 to thereby fill the second interconnect trench 221 and the via hole 222 with the Cu plating film 228. After that, as shown in FIG. 1D, the Cu plating film 228, the Ta barrier film 226 and the TaN barrier film 225 are polished back by a CMP method to flatten the surface of the substrate, thereby forming a second Cu interconnect layer 223 and a Cu via 224 as a second interconnect layer.
As described above, multi-layer interconnects having a so-called dual damascene structure is realized by employing Cu to form the first interconnect layer, the second interconnect layer and the via metal. However, in the configuration of multi-layer interconnects, a laminated barrier film consisting of TaN and Ta is formed at an interface between Cu and an interlayer insulation film and therefore, diffusion of Cu atoms into the interlayer insulation film can be prevented, and as a result, Cu contamination observed in a situation where diffusion of Cu into an adjacent interconnect layer and/or an element, both being located next to a certain interconnect layer in problem, causes short circuit between interconnect layers and/or deterioration in the element's performance can also be prevented. In addition, since Ta is adherently bonded to both Cu and TaN, disposing Ta between Cu and TaN resultantly improves adherence between Cu and TaN, as well as adherence between Cu and an interlayer insulation film. This construction of multi-layer interconnects solves the following drawbacks found in the conventional technique. That is, when polishing a surface of the substrate to flatten the surface thereof by using the above-mentioned CMP method, polishing slurry enters an interface between Cu and an interlayer insulation film to deteriorate adherence therebetween and mechanical stress imparted to Cu and the interlayer insulation film during polishing operation deteriorate adherence therebetween to thereby remove a Cu interconnect layer from the interlayer insulation film.
As described above, forming a laminated barrier film consisting of Ta and TaN at an interface between an interlayer insulation film and Cu makes it possible to effectively prevent diffusion and removal of Cu. However, it should be noted here that when focusing on a Cu via 224, which is shown in FIGS. 1A through 1D and has such laminated barrier film thereunder, the first interconnect layer, i.e., the first Cu interconnect layer 212, formed under the Cu via 224 and facing the bottom surface of the Cu via 224 is constructed such that the TaN barrier film 225 is formed on and in contact with the upper surface of the first Cu interconnect layer 212. As is already mentioned, the TaN barrier film 225 is weakly bonded to Cu and therefore, when passing a current from the second Cu interconnect layer 223 through the Cu via 224 to the first Cu interconnect layer 212, electro-migration occurs at an interface between Cu of the first Cu interconnect layer 212 and the TaN barrier film 225 in the following manner. That is, Cu atoms existing in the upper portion of the first Cu interconnect layer 212 move along an interface between the first Cu interconnect layer 212 and the TaN barrier film 225 to the other area while removing Cu existing in the surface portion of the first Cu interconnect layer 212 and located under the bottom surface of the Cu via 224, in other words, producing voids in the surface portion thereof, resulting in loss of adherence between the TaN barrier film 225 and the first Cu interconnect layer 212 and increase in contact resistance therebetween. In addition, thermal stress imparted to the multi-layer interconnects during manufacturing steps also deteriorates adherence between the first Cu interconnect layer 212 and the TaN barrier film 225 at an interface therebetween to thereby increase contact resistance therebetween.